Verify your generated HDL more quickly, and with greater confidence using CoValidator HDL test bench generator. Impulse CoValidator is a faster way to generate HDL simulation test benches for FPGA design. CoValidator provides a fast path from C to hardware-accurate and bit-accurate RTL simulation, without writing HDL. Use CoValidator with Impulse C™ to design and simulate FPGA hardware, using familiar software programming methods.

CoValidator generates HDL compatible with all IEEE-compliant VHDL simulators, and also generates scripts for ModelSim®, allowing you to generate HDL test benches and launch simulation with just a few keystrokes. Catch errors before place-and-route, saving hours, days or even weeks of development time. Generate an HDL test bench, data files, and simulator scripts for hardware validation and hardware/software equivalency checking.

• Design your complex, streaming algorithms using Impulse C.
• Validate correct untimed algorithm behavior with standard C compilers and debuggers such as Visual Studio, Eclipse, or GCC
• Refactor, optimize and compile your C code to create synthesis-ready HDL.
• Verify the generated HDL using industry-standard RTL simulators, and using automatically generated HDL test benches, before synthesizing the HDL to a target FPGA device.

CoValidator is ideal for image and video processing, DSP, and other high-throughput streaming applications.

Contact us for pricing and other details.

Note: ModelSim is a registered trademark of Mentor Graphics Corporation