Tutorials and Resources for Altera Nios II Embedded
Evaluation Kit, Cyclone III Edition
| Platform Summary - Cyclone III EP3C25F424 FPGA Device - 32MB DDR SDRAM - 1MB synchronous SRAM - 16 MB Intel P30/P33 flash - Color LCD 800 x 480 touch-screen display - 10/100 Ethernet PHY/MAC - 16Mx8 parallel/BPI configuration flash - 24-bit CD-quality audio CODEC - Audio-out, audio-in, microphone-in ports - RS-232 serial port - Composite TV input - General Purpose I/O: buttons, LEDs, and DIP switches - Example applications and tutorials Compatible Platform Support Packages - Altera Generic VHDL - Altera Generic Verilog - Altera Nios II Avalon (VHDL) Step-by-Step Tutorials Using CoDeveloper with the Altera Nios II processor This example demonstrates the use of the Nios II processor and Avalon interface for coprocessor acceleration. Hello World Tutorial for Nios II Evaluation Kit, Cyclone III Edition FIR Filter Tutorial for Nios II Evaluation Kit, Cyclone III Edition Other Resources Altera Website Nios II Evaluation Kit, Cyclone III Edition Specifications See Also Tutorials for XtremeData FPGA Platforms |
 Nios II Embedded Evaluation Kit, Cyclone III Edition Available from Altera and its authorized resellers |